Not applicable.
Not applicable.
1. Field of the Invention
The present invention generally relates to setting the speed of a central processing unit in a computer system. More specifically, the invention relates to detecting whether the computer system central processing unit has changed, and if so, prompting the computer system user to enter a correct processing unit speed.
2. Background of the Invention
In the early days of computer system technology, motherboards (which are the main circuit boards in computers on which most of the core electronics are mounted) were built for use with a particular central processing unit (CPU). In some instances in early computers, the CPU was hard-wired or soldered to the motherboard such that it was not easily removable. As computer system technology advanced, motherboard manufacturers began to design motherboards that could be used with different central processing units. In this way, the manufacturer could support multiple types of CPUs with a single motherboard to aid in keeping the manufacturer competitive.
Different CPUs each may operate at different speeds. The speed of operation of a CPU is termed its xe2x80x9cfrequencyxe2x80x9d and is determined by a clock signal provided to it. The clock signal is a periodic signal that transitions through many cycles each second. For example, a 500 MHz clock signal transitions through 500 million periodic cycles each second. The clock signal provided to the CPU typically is generated by specialized devices separate from the CPU and routed to the CPU chip via a conductive trace on the computer""s motherboard. In making a motherboard capable of supporting various types of CPUs, each motherboard manufacturer had to address supporting CPUs having different operational speeds. In supporting CPUs having various operational speeds, some mechanism had to exist to modify operation of the motherboard such that it clocked the CPU at the proper speed. Early implementations used jumpers or dip switches to indicate to the motherboard which CPU was in place, and at what speed the CPU was to operate. These jumpers or dip switches may have set or changed voltage levels or may have controlled or set clock frequency.
The xe2x80x9chostxe2x80x9d bus generally is the bus which couples the CPU to other devices in the computer and across which the CPU communicates. One of the signals comprising the host bus is a clock signal, and the CPU uses that clock signal for its own use to generate a clock signal to operate the CPU""s core logic (or simply xe2x80x9ccorexe2x80x9d). With advancement in microprocessor technology, the microprocessors themselves became capable of specifying the frequency of the clock signal for the host bus. However, a second set of parameters was established which determined the speed at which the CPU core was clocked. More specifically, the second set of parameters determined the ratio of the clock frequency of the host bus to the core operating frequency of the CPU. The ratio thus specified how fast the core of the CPU should be clocked relative to the clock frequency of the host bus For example, if the host bus speed was 66 MHz, and the host bus to core ratio was ⅙, the processor core operated at 400 MHz. Jumpers and dip switches used by prior art devices set this host bus to core frequency ratio. FIG. 1 shows one prior art structure for setting the host bus to CPU core frequency ratio. Shown in FIG. 1 is a multiplexer 10 located between a CPU 12 and bridge device 14. The multiplexer 10 connects either the four signal lines 11 from the bridge 14, or the four signal lines 17 from the switch bank 16, to the four lines 13 routed to the CPU 12. In normal operation, the bridge device 14 communicated directly with the CPU 12, across the four signal lines 11 to perform functions other than setting the host bus to CPU core frequency ratio. However, during power up, it was necessary to selectively assert lines 13 to indicate to the CPU the correct host bus-to-core speed ratio. As indicated in FIG. 1, this was accomplished by having the switch bank 16, which possibly comprised dip switches or jumpers, connected to the multiplexer 10 such that during the power up procedure, the multiplexer coupled signals 17 from the switch bank 16 to the CPU 12. At this point during power up, the state of signals 17/13 indicated the desired clock frequency ratio. After informing the CPU 12 of its correct host bus-to-CPU core frequency, the multiplexer 10 shifted back to coupling the four output signal lines from the bridge 14 to the CPU 12 for normal operation.
The next development in setting the host bus-to-CPU core frequency ratio came with a chip-set manufactured by Intel(trademark) Corporation. Intel(trademark) effectively replaced the switch bank 16 and multiplexer 10 with registers in the Intel(trademark) Input/Output Controller Hub (xe2x80x9cICHxe2x80x9d), the equivalent of the bridge device 14. Rather than have a switch bank 16, strap registers existed within the ICH which coupled to the CPU 12 through a multiplexer, or its equivalent, that was internal to the ICH. In this way, the same functionality was accomplished, yet that functionality was contained within the ICH. However, by placing the switch bank and multiplexers within Intel""s bridge device, this effectively removed the mechanism for a person working on the computer system to inform the motherboard of a change of the CPU. Consequently, the working CPU could change, but the indication of host-to-core frequency in the bridge device still reflect old values. This could lead to processing errors if the new CPU is operated beyond its functional limits or non-optimum performance if the CPU is operated below its rated maximum.
It would be desirable to detect when the computer system""s CPU has been removed and replaced. Further, it would be desirable to provide a convenient mechanism by which the contents of the strap registers may be changed responsive to removal and replacement of the computer system""s CPU.
The problems noted above are solved in large part by a detection circuit that can detect when the CPU of a computer system has been removed, even if that removal occurs during a time when the computer system is powered off. The detection circuit comprises a pull-up resistor connected on one side to a battery voltage and on its other side to both a grounded pin of the CPU as well as an input signal line of a super input/output (I/O) controller. When the CPU is in place, the grounded pin of the CPU effectively grounds a side of the pull-up resistor opposite that of the battery. However, when the CPU is removed, the CPU side of the resistor rises in voltage to a level that approaches that of the battery. When this high voltage condition occurs, the super I/O controller latches an indication that the CPU has been removed.
Upon subsequent power up, the super I/O controller indicates to a bridge logic device, which may comprise an I/O controller hub (ICH), that the computer system CPU has changed since the last operation. In response, the ICH operates the CPU at a reduced, default frequency to ensure correct operation. Software executed during the power on self test (POST) procedure prompts the computer system user for a correct host bus to core frequency ratio. Once entered, the software writes the new value, if required, to strap registers in the ICH and then reboots the computer. Upon the next power up procedure, the correct host bus to CPU operating frequency is passed to the CPU for correct operation.
Thus, the preferred embodiment of the invention addresses the problem that arises when a CPU is replaced in a computer system where the host-to-core frequency ratio is set otherwise automatically by an ICH. If the system is unable to detect a change of the CPU, which is the case in the prior art, then the possibility exists that strap registers in the ICH may not reflect the true host-to-core ratio.